Semiconductor structures, such as, integrated circuits are formed from semiconductor substrates within and upon whose surfaces may be formed electrical circuit elements such as transistors including field-effect transistors (FETs). Conventionally, field-effect transistors have been fabricated as planar circuit elements.
Fin field-effect transistor (FinFET) devices are currently being developed to replace conventional planar transistors, such as metal oxide semiconductor field-effect transistors (MOSFETs), in advanced complementary metal oxide semiconductor (CMOS) technology, due to their improved short channel effect immunity and higher on-current to off-current ratio (Ion/Ioff). As is known, the term “fin” refers to a vertical structure within or upon which are formed, for instance, one or more FinFETs or other fin devices, such as passive devices, including capacitors, diodes etc.
As described by Moore's Law, the semiconductor industry drives down pattern dimensions in order to reduce transistor size and enhance processor speed at a rapid pace. Further enhancements in fin device structures and fabrication methods therefor continue to be pursued for enhanced performance and commercial advantage. As the size of transistors, and components such as fin width and pitch, are reduced, obstacles pertaining to punchthrough of current may be encountered, hampering attempts to further reduce scale. The use of super steep retrograde wells (SSRW) in transistor design may ameliorate these difficulties, but conventional methodologies for forming SSRW preclude adopting fin widths and pitches below a certain minimum. Thus, an improved method for forming SSWR is needed.